Resume: Jared Mason Buckner
jaredbuckner[AT]gmail[DOT]com
http://buckner.dnsalias.net/resume.html
Talented design engineer with 6+ years experience in leading technology centers. Innovator with a wide range of skills in ASIC, telecom, and software design.
Somerset Design Center, Austin, Texas
Currently leading the development of a new circuit optimization framework
which simultaneously integrates gate sizing, switching thresholds, power
consumption, and area. Co-developed a new method to model and time footless
domino logic within the static timing framework. Designed, developed, and
fully documented a C++ applilcation programming interface to Freescale's
high-performance static timing analyzer, enabling the development of
pluggable
client programs for custom analysis; this allowed Freescale to
use the timer to be rolled out globally. Further maintained, supported, and
extended Freescale's internal high-performance static timing analysis tool.
Analyzed performance and accuracy of timing models with respect to SPICE.
StarCore Design Center, Atlanta, Georgia
Integrated modules on Digital Signal Processor (DSP) cores and analyzed resultant designs for timing and functional errors. Synthesized module designs into placed, routed gate-level descriptions suitable for manufacture. Debugged RTL descriptions. Managed project constraints and design data, including communicating with customers on design requirements and issues. Captured design and analysis methodology with documentation, custom software, and makefiles. Developed many tools that greatly reduced time between design iterations.
Boynton Cellular Design Center, Boynton Beach, Florida
Designed and tested peripheral support circuitry for the baseband processor controlling a tri-band GSM phone. Managed integration of software development platform and tools into phone design. Developed composite antenna patterns for cellular applications, including RF planning simulations, subscriber unit field patterns, etc. Involved in the investigation of RF propagation dynamics in multi-scattering environments with respect to cellular systems.
StarCore Design Center, Motorola, Atlanta, Georgia
Designed automated verification system to fully test Verilog design of a DSP core. Verification design was a multi-processor parallel system written in Perl. Assisted with integration of code coverage tools into verification system.
Performed PC support for the School of Civil Engineering. Installed and repaired computer software and hardware, including IBM-compatible, Macintosh, and Unix computers and related peripherals. Maintained approximately 300 computers school-wide. Instructed students in the basic use of applications such as Microsoft Excel, Microsoft Word, Netscape Navigator, and Adobe Acrobat.
Documented internal operation of the 8600x cable settop. Organized transaction specification into an 80-page handbook used by software engineers to assist development of the product. Assisted the development of a demonstration system for a national convention. Successfully proposed a new automated testing system (ATS) to speed up the debugging process during alpha testing. Wrote Visual Basic 5 code for use in Windows as part of the team developing the new ATS. Wrote C code to compress text strings in the 8600x.
Bachelors of Electrical Engineering
Georgia Institute of Technology, Atlanta, Georgia
Degree Granted: December 1999
Specialization: Digital Signal Processing and Telecommunications
Coursework covered:
References Available on Request